ics674-01 user configurable divider mds 674-01 a 1 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information ? packaged as 28 pin ssop (150 mil body) ? supports ics673 pll building block ? user determines the divide by setting input pins ? pull-ups on all select inputs ? includes one 7-bit divider for outa ? includes one 9-bit divider and one selectable post divider for outb ? operating voltages of 3.3 v or 5.0 v ? industrial temperature range available ? 25ma drive capability at ttl levels ? advanced, low power cmos process the ics674-01 consists of 2 separate configurable dividers. the a divider is a 7 bit divider and can divide by 3 to 129. the b divider consists of a 9 bit divider followed by a post divider. the 9 bit divider can divide by 12 to 519. the post divider has eight settings of 1, 2, 4, 5, 6, 7, 8 and 10 giving a maximum total divide of 5190. the a and b dividers can be cascaded to give a maximum divide of 669510. the ics674-01 supports the ics673 pll building block and enables the user to build a full custom pll synthesizer. block diagram description features divider a (7-bit) output buffer post divider divider b (9-bit) 7 2 3 vdd gnd ina inb outa outb b8:b0 a6:a0 93 s2:s0 output buffer
ics674-01 user configurable divider mds 674-01 a 2 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information pin assignment key: i(pu) = input with internal pull-up resistor; i=input (no pull-up); o = output; p = power su pp ly connection 1 8 9 2 3 4 5 6 7 10 11 12 13 14 16 15 20 17 18 19 25 24 23 22 21 26 27 28 b2 inb vdd ina gnd b4 vdd outa gnd a2 a4 b8 outb a3 a1 b6 b5 gnd a0 pin # name type description 1, 2, 24-28 a5, a6, a0-a4 i(pu) divider a word input pins. forms a binary number from 3 to 129. 3, 4, 5 s0, s1, s2 i(pu) select pins for post divider. see table above. 6, 23 vdd p connect to vdd. 7 ina i divider a input. 8 inb i divider b input. 9, 19, 20 gnd p connect to ground. 10-18 b0-b8 i(pu) divider b word input pins. forms a binary number from 12 to 519. 21 outb o divider b output. 22 outa o divider a out p ut. a5 a6 b0 b3 b1 s2 s0 s1 b7 s2 s1 s0 post pin 5 pin 4 pin 3 divide 000 10 001 2 010 8 011 4 100 5 101 7 110 1 111 6 post divider table pin description external components the ics674-01 requires a 0.01f decoupling capacitor to be connected between vdd and gnd. it must be connected close to the ics674-01 to minimize lead inductance. terminating resistors of 33 w can be used in series with the outa and outb p ins.
ics674-01 user configurable divider mds 674-01 a 3 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information determining (setting) the divider the user has full control in setting the desired divide. the user should connect the appropriate divider select input pins directly to ground (or vdd, although this is not required because of internal pull-ups) during printed circuit board layout, so that the ics674-01 automatically produces the correct divide when all components are soldered. it is also possible to connect the inputs to parallel i/o ports in order to change divides. the divides of the ics674-01 can be determined by the following simple equations: divide a = daw+2 where divider a word (daw) = 1 to 127 (0 is not permitted). divide b = (dbw+8)?pd where divider b word (dbw) = 4 to 511 (0,1,2,3, are not permitted). post divider (pd) = values on page 2 for example, suppose divide a is desired to be 61 and divide b is desired to be 284, then daw = 59, dbw = 276 and pd = 1. this means a6:a0 is 0111011, b8:b0 is 100010100 and s2:s0 is 110. since all inputs have pull-ups, it is only necessary to ground the zero pins, namely a6, a2, b7, b6, b5, b3, b1, b0 and s0.
ics674-01 user configurable divider mds 674-01 a 4 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information output clock divide a refin fbin ics673-01 clk1 clk2 divide b post divide reference clock if the reference is in the khz range, for example 8 khz, the following configuration may be more ty p ical: output clock divide a refin fbin ics673-01 clk1 clk2 divide b post divide reference clock note that in both examples divide b is connected to the output of the ics673. this is because divide b has a hi g her o p eratin g fre q uency than divide a. usin g the ics674-01 with the ics673-01: the ics674-01 may be used with the ics673-01 to build a frequency synthesizer. the following example shows a ty p ical a pp lication when the reference clock is in the mhz ran g e: ics674-01 ics674-01
ics674-01 user configurable divider mds 674-01 a 5 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information parameter conditions minimum typical maximum units absolute maximum ratings (stresses be o o nd these can p ermanentl dama g e the d e e vice) supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+0.5 v clock output referenced to gnd -0.5 vdd+0.5 v ambient operating temperature 0 70 c ambient operating temperature i version -40 85 c soldering temperature max of 10 seconds 260 c storage temperature -65 150 c dc characteristics (vdd = 5.0v unless ot h h erwise noted) operating voltage, vdd 3 5.5 v input high voltage, vih all a, b, and s pins 2 v input low voltage, vil all a, b, and s pins 0.8 v input high voltage, vih, ina and inb only (vdd/2)+1 vdd/2 v input low voltage, vil, ina and inb only vdd/2 (vdd/2)-1 v output high voltage, voh ioh=-25ma 2.4 v output low voltage, vol iol=25ma 0.4 v idd, op. supply cur., diva=divb=20 at 3.3 v no load, fin=100 mhz 3 ma idd, op. supply cur., diva=divb=20 at 5 v no load, fin=100 mhz 5 ma short circuit current, outputs 70 ma on-chip pull-up resistor a, b, s select pins 270 k w input capacitance a, b, s select pins 5 pf ac characteristics (vdd = 5.0v unless ot h h erwise noted) input frequency, divider a at 3.3 v 0 135 mhz input frequency, divider b at 3.3 v 0 180 mhz input frequency, divider a at 5 v 0 200 mhz input frequency, divider b at 5 v 0 235 mhz input frequency, divider a (industrial temperature) at 3.3 v at 85 c 0 125 mhz input frequency, divider b (industrial temperature) at 3.3 v at 85 c 0 170 mhz input frequency, divider a (industrial temperature) at 5 v at 85 c 0 190 mhz input frequency, divider b (industrial temperature) at 5 v at 85 c 0 220 mhz output clock rise time 0.8 to 2.0v 1 ns output clock fall time 2.0 to 0.8v 1 ns outb clock duty cycle (see note) at vdd/2 45 49 to 51 55 % outb clock duty cycle, odd post dividers at vdd/2, except pd=1 40 60 % outa clock duty cycle (see note) at vdd/2 20 98.5 % note: the duty cycle of outa is dependent on the selected divide. this is because outa goes low for 2 input clock cycles on ina. so, for example, if a divide of 20 is selected, the duty cycle will be 90%. similarly, if pd=1 is selected for outb, the duty cycle will be dependent on the selected divide. in this case outb g oes hi g h for a pp roximately 8 in p ut clock cycles on inb.
ics674-01 user configurable divider mds 674-01 a 6 revision 033199 printed 11/15/00 inte g rated circuit systems ? 525 race street ? san jose ? ca ? 95126 ?(408)295-9800tel?(408)295-9818fax preliminary information while the information presented herein has been checked for both accuracy and reliability, ics assumes no responsibility for ei ther its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this pro duct is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environment al requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not au thorize or warrant any ics product for use in life support devices or critical medical instruments. package outline and package dimensions b d eh e q c h x 45 l 28 pin ssop inch e e s milli m m eters symbol min max min max a 0.061 0.068 1.55 1.73 b 0.008 0.012 0.203 0.305 c 0.007 0.010 0.191 0.254 d 0.385 0.400 9.779 10.160 e 0.150 0.160 3.810 4.064 h 0.230 0.245 5.842 6.223 e .025 b s s c 0.635 b b sc h 0.016 0.406 q 0.004 0.01 0.102 0.254 l 0.016 0.035 0.406 0.889 ordering information part/order number marking * package temperature ICS674R-01 674r-01 28 pin narrow ssop 0 to 70 c ICS674R-01t 674r-01 28 pin ssop on tape and reel 0 to 70 c ICS674R-01i 674r-01i 28 pin narrow ssop -40 to 85 c ICS674R-01it 674r-01i 28 p in ssop on ta p e and reel -40 to 85 c * this shows the top line marking. the part will have the letters ics in a box on the upper left hand corner.
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